We spent the past two weeks verifying Xilinx ISE 12.2 (M.63c).  The installations went without incident on our RHEL5 64b WS platforms. We kicked off the standard verification and build regressions and encountered only minor issues. No source code changes were needed. Functional simulation with ISim continues to work correctly and quickly. Board and substrate testing focused on the ML605, XUPV5, ML555, SX95T and LX330T.

As planned, we now “bless”  ISE-LOGIC 12.2 as the default simulation and build environment for OpenCPI applications using Xilinx FPGAs.

Shep Siegel developers, opencpi fpga V5 hardware, fpga v6 hardware, ISE 12.x, opencpi

We now have seven of eleven chosen board targets working with our default DMA loopback application. Other OpenCPI  developers are going down their own private paths, as well. It is exciting that we can see our IP “travel“, but much work remains in the form of build automation. OpenCPI is, after all, in the business of component portability!

There will be some re-factoring to allow for better decoupling of Boards, (FPGA) Substrates, and Application Containers. We have our eye on several aspects which include: Bottom-Up and Top-Down composition, Verification, Synthesizable Assertion Monitors, Static and Dynamic HDL code structure.

Hang tight as we work in the weeks ahead to merge the software and hardware code branches. We expect this site to remain the launch pad. We have been working towards pushing tactical builds to http://github.com/opencpi/opencpi (which makes sense, since we are using git for version control). But for the next few weeks, the most-tactical builds may often be from the responsible software or hardware lead.

We are planning for another glossing in early August, immediately following the public release of Xilinx ISE 12.2. And after our regressions show all is well.

Shep Siegel developers, opencpi fpga V5 hardware, fpga v6 hardware, ISE 12.x, OpenCPI Boards