We now have seven of eleven chosen board targets working with our default DMA loopback application. Other OpenCPI developers are going down their own private paths, as well. It is exciting that we can see our IP “travel“, but much work remains in the form of build automation. OpenCPI is, after all, in the business of component portability!
There will be some re-factoring to allow for better decoupling of Boards, (FPGA) Substrates, and Application Containers. We have our eye on several aspects which include: Bottom-Up and Top-Down composition, Verification, Synthesizable Assertion Monitors, Static and Dynamic HDL code structure.
Hang tight as we work in the weeks ahead to merge the software and hardware code branches. We expect this site to remain the launch pad. We have been working towards pushing tactical builds to http://github.com/opencpi/opencpi (which makes sense, since we are using git for version control). But for the next few weeks, the most-tactical builds may often be from the responsible software or hardware lead.
We are planning for another glossing in early August, immediately following the public release of Xilinx ISE 12.2. And after our regressions show all is well.
Shep Siegel developers, opencpi fpga V5 hardware, fpga v6 hardware, ISE 12.x, OpenCPI Boards
Xilinx yesterday (2010-04-27) provided us early-access to ISE 12.1 (M.53d) which we promptly installed on four development machines. The installations went without incident on our RHEL5 64b platforms. We kicked off the standard verification and build regressions and encountered but one unexpected issue: The PAR cost table switch “-t” has moved back into MAP and now has a sibling “-xt”.
Functional simulation with ISim has, and continues, to work correctly and quickly.
The V5 SX95T generic bitstreams built without incident (similar QoR; slightly quicker builds) and ran on the target V5 platforms without incident through the PCIe DMA test regressions.
The V6 LX240T (ML605) bitstreams required a minor migration from MIG 3.3 to MIG 3.4 to support the DDR3 SDRAM. We also migrated the V6 PCIe hardcore endpoint wrapper from v1.4 to v1.5. We made these changes, built the bitstreams, and ran on the target V6 platforms without incident. The on-bench hardware testing included PCIe DMA and DDR3 SDRAM memory tests.
As planned, we expect to make ISE-LOGIC 12.1 the default simulation and build environment for OpenCPI applications using Xilinx FPGAs, as soon as Xilinx releases 12.1 to the public.
Shep Siegel developers, opencpi fpga V5 hardware, fpga v6 hardware
ISE 11.4 support is now available for Xilinx-based OpenCPI platforms. We ran the PIO and DMA regressions last night against oc1001-ml555, and have a deeper regression suite planned for the upcoming weekend. There were only minor issues related to the PCIe endpoint. QoR and runtime are essentially unchanged.
Shep Siegel developers, opencpi fpga V5 hardware, fpga v6 hardware
Avnet delivered Atomic Rules’ first ML605 board last Friday afternoon. Although no core OpenCPI code change was needed, there were several Xilinx tool scripting issues (V6 specific) that we resolved. We ran all of our PCIe passive and DMA regressions with the ML605. It was tested interacting with the host; and peer-peer DMA with an ML555. It is fully-functional and observed identical to our ML555, XUPV5, ALDER, and SX95T regressions. All simulations were done with ISim, all RTL synthesis with XST.
Shep Siegel developers, opencpi fpga v6 hardware
