There will be some re-factoring to allow for better decoupling of Boards, (FPGA) Substrates, and Application Containers. We have our eye on several aspects which include: Bottom-Up and Top-Down composition, Verification, Synthesizable Assertion Monitors, Static and Dynamic HDL code structure.

Hang tight as we work in the weeks ahead to merge the software and hardware code branches. We expect this site to remain the launch pad. We have been working towards pushing tactical builds to http://github.com/opencpi/opencpi (which makes sense, since we are using git for version control). But for the next few weeks, the most-tactical builds may often be from the responsible software or hardware lead.

We are planning for another glossing in early August, immediately following the public release of Xilinx ISE 12.2. And after our regressions show all is well.

Functional simulation with ISim has, and continues, to work correctly and quickly.

The V5 SX95T generic bitstreams built without incident (similar QoR; slightly quicker builds) and ran on the target V5 platforms without incident through the PCIe DMA test regressions.

The V6 LX240T (ML605) bitstreams required a minor migration from MIG 3.3 to MIG 3.4 to support the DDR3 SDRAM. We also migrated the V6 PCIe hardcore endpoint wrapper from v1.4 to v1.5.  We made these changes, built the bitstreams, and ran on the target V6 platforms without incident. The on-bench hardware testing included PCIe DMA and DDR3 SDRAM memory tests.

As planned, we expect to make ISE-LOGIC 12.1 the default simulation and build environment for OpenCPI applications using Xilinx FPGAs, as soon as Xilinx releases 12.1 to the public.