12/21/2010

OpenCPI now supports Xilinx ISE 12.4

Over the past week we have been testing Xilinx ISE 12.4 (M.81d). The installations went without incident on our RHEL5 64b WS platforms. We kicked off the standard verification and build regressions and encountered no issues. No source code changes were needed. Functional simulation with ISim works correctly and quickly. Due to finite resources, board and substrate testing was focused on the V6-LX240T of the ML605. With testing of the V5 boards (XUPV5, ML555, SX95T and LX330T) taking a lower priority. We noted no substantial changes in runtime or QoR.

Between production 12.3 and production 12.4, user-compiled code for XST libraries may not be compatible. If you fail to rebuild your XST libs; we have evidence that you may yield an incorrect circuit. However, if you simply rebuild any user-supplied RTL with ISE/XST 12.4, all is good. (OpenCPI pre-compiles Verilog primitives into libraries to speed XST synthesis).

As planned, we now .bless. ISE-LOGIC 12.4 as the default simulation and build environment for OpenCPI applications using Xilinx FPGAs. We continue to support 12.3, but deprecate its use.