Xilinx has bumped the Gen-2 PCIe core to revision 1.4 in ISE 11.4, and the latest drop of OpenCPI supports Gen2 operation with the ML605. We are working with Xilinx to ensure a smooth transition to ISE 12 as soon as it becomes public. A short video of three development systems is linked here.
ISE 11.4 support is now available for Xilinx-based OpenCPI platforms. We ran the PIO and DMA regressions last night against oc1001-ml555, and have a deeper regression suite planned for the upcoming weekend. There were only minor issues related to the PCIe endpoint. QoR and runtime are essentially unchanged.
Avnet delivered Atomic Rules’ first ML605 board last Friday afternoon. Although no core OpenCPI code change was needed, there were several Xilinx tool scripting issues (V6 specific) that we resolved. We ran all of our PCIe passive and DMA regressions with the ML605. It was tested interacting with the host; and peer-peer DMA with an ML555. It is fully-functional and observed identical to our ML555, XUPV5, ALDER, and SX95T regressions. All simulations were done with ISim, all RTL synthesis with XST.
Although not yet merged into the mainline, or formally committed to, the Xilinx XUPV5-LX110T board has been seen running the “oc1001″ reference application against the rplTest regressions. More details over at: http://atomicrules.blogspot.com/2009/10/more-boards-less-risk.html
