OpenCPI now supports Xilinx ISE 12.1
Xilinx yesterday (2010-04-27) provided us early-access to ISE 12.1 (M.53d) which we promptly installed on four development machines. The installations went without incident on our RHEL5 64b platforms. We kicked off the standard verification and build regressions and encountered but one unexpected issue: The PAR cost table switch “-t” has moved back into MAP and now has a sibling “-xt”.
Functional simulation with ISim has, and continues, to work correctly and quickly.
The V5 SX95T generic bitstreams built without incident (similar QoR; slightly quicker builds) and ran on the target V5 platforms without incident through the PCIe DMA test regressions.
The V6 LX240T (ML605) bitstreams required a minor migration from MIG 3.3 to MIG 3.4 to support the DDR3 SDRAM. We also migrated the V6 PCIe hardcore endpoint wrapper from v1.4 to v1.5. We made these changes, built the bitstreams, and ran on the target V6 platforms without incident. The on-bench hardware testing included PCIe DMA and DDR3 SDRAM memory tests.
As planned, we expect to make ISE-LOGIC 12.1 the default simulation and build environment for OpenCPI applications using Xilinx FPGAs, as soon as Xilinx releases 12.1 to the public.
